{"id":1133,"date":"2026-11-10T05:53:38","date_gmt":"2026-11-10T05:53:38","guid":{"rendered":"https:\/\/tlindner.macmess.org\/?p=1133"},"modified":"2026-11-10T05:53:38","modified_gmt":"2026-11-10T05:53:38","slug":"ensoniq-mirage-measurements-wanted","status":"publish","type":"post","link":"https:\/\/tlindner.macmess.org\/?p=1133","title":{"rendered":"Ensoniq Mirage: Measurements Wanted"},"content":{"rendered":"

Ensoniq Mirage: Measurements Wanted<\/h1>\n

Why these measurements<\/h2>\n

MAME’s Ensoniq Mirage emulation (ensoniq\/enmirage.cpp<\/code>, sound\/cem3328.cpp<\/code>) works, but several of its numbers are estimates from the schematic and datasheets. Each measurement below replaces one of those estimates with a real value. The most valuable are marked priority<\/strong>.<\/p>\n

Part numbers and pins refer to the DSK-8 main board schematic, drawing 4010003401, sheets 1 (analog, rev G, 1985) and 2 (digital). Please note your board’s revision if it differs.<\/p>\n

Equipment:<\/strong> a two-channel oscilloscope (20 MHz or better), a multimeter, a MIDI interface, and a Mirage OS boot disk. A frequency counter or a scope with a frequency readout saves time.<\/p>\n

Safety:<\/strong> the power supply carries mains voltage. Everything here is on the main board’s low-voltage side (+5 V, +12 V, ?8 V). Clip the scope ground to board ground, never to a supply rail.<\/p>\n

1. VIA and MIDI clocks (priority)<\/h2>\n

These confirm that the 6522 VIA runs at 2 MHz and that its PB7 output makes the 500 kHz MIDI clock. MAME’s change to the 6522 core rests on this. Measure after the OS has loaded from disk.<\/p>\n\n\n\n\n\n\n\n\n\n
Signal<\/th>\nWhere<\/th>\nRecord<\/th>\nExpected<\/th>\n<\/tr>\n<\/thead>\n
CAS (VIA ?2)<\/td>\nU9 pin 25, also U12 pin 14<\/td>\nFrequency, duty cycle<\/td>\n2 MHz<\/td>\n<\/tr>\n
CPU E (ED)<\/td>\nU15 pin 34<\/td>\nFrequency, phase relative to CAS<\/td>\n2 MHz<\/td>\n<\/tr>\n
SERCLK (VIA PB7)<\/td>\nU9 pin 17, also U12 pins 3 and 4<\/td>\nFrequency, duty cycle<\/td>\n500 kHz square wave<\/td>\n<\/tr>\n
CA3 (to VIA PB5)<\/td>\nU9 pin 15<\/td>\nFrequency<\/td>\n500 kHz (8 MHz \u00f7 16)<\/td>\n<\/tr>\n
8 MHz master<\/td>\nU11 or U13 clock input<\/td>\nFrequency<\/td>\n8 MHz<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Also useful: whether SERCLK is present before the disk loads, and when it first starts.<\/p>\n

2. Filter control voltages<\/h2>\n

These check the chain from the CV DAC (U41, AD7524) to each filter’s control pins. The emulation assumes the DAC spans 0 to +5.08 V (about 19.9 mV per step) and that the hold buffers have unity gain.<\/p>\n\n\n\n\n\n\n\n\n\n\n
Signal<\/th>\nWhere<\/th>\nRecord<\/th>\nExpected<\/th>\n<\/tr>\n<\/thead>\n
DAC reference (CVREF)<\/td>\nU41 pin 15<\/td>\nDC voltage<\/td>\n?5.1 V (zener CR4)<\/td>\n<\/tr>\n
CV I\/V output<\/td>\nU56 pin 14<\/td>\nWaveform: the DAC steps as each voice is refreshed<\/td>\n0 to +5.08 V<\/td>\n<\/tr>\n
Held cutoff, voice 1 (VF1)<\/td>\nU61 pin 8<\/td>\nDC level and droop between refreshes (AC-coupled)<\/td>\nSteady; droop under 1 step<\/td>\n<\/tr>\n
Held resonance, voice 1 (VQ1)<\/td>\nU66 pin 8<\/td>\nDC level<\/td>\n0 to +5.08 V<\/td>\n<\/tr>\n
CEM3328 pin 2, voice 1<\/td>\nU67 pin 2<\/td>\nDC level, with VF1 measured at the same moment<\/td>\n0.0355 \u00d7 VF1 ? 0.048 V<\/td>\n<\/tr>\n
CEM3328 pin 3 (I_REF), voice 1<\/td>\nU67 pin 3<\/td>\nDC level<\/td>\nAbout ?7.3 V<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

The pin 2 line is the most useful: three or four readings of VF1 against pin 2 confirm the 27K \/ 160K \/ 1K network.<\/p>\n

3. CEM3328 filter response (priority)<\/h2>\n

The filter model uses the datasheet’s typical figures: 20 mV per octave, and about 105 Hz at 0 V on pin 2 with the Mirage’s parts. A self-oscillating filter makes a clean sine at its cutoff, so its frequency can be read straight off the output.<\/p>\n

    \n
  1. Cutoff curve.<\/strong> Set a sound’s resonance to maximum so voice 1 oscillates. Step the filter cutoff parameter through five or more values from low to high. At each step record U67 pin 2 (DC) and the frequency at U67 pin 9 (output). This gives the real scale factor and base frequency.<\/li>\n
  2. Oscillation threshold.<\/strong> With the cutoff mid-range, raise resonance one step at a time. Record U67 pin 10 at the first step that oscillates. Datasheet: 2.7 to 3.7 V, typically 3.2 V.<\/li>\n
  3. Oscillation level.<\/strong> At maximum resonance, record the peak-to-peak voltage at U67 pin 9. Datasheet: about 2.3 V.<\/li>\n
  4. Resonance curve.<\/strong> At three or four resonance settings below oscillation, play a note and record the output level relative to resonance off. The datasheet only calls this a “reverse audio taper”, and the model’s curve is a guess.<\/li>\n
  5. Voice-to-voice spread.<\/strong> With all voices at the same cutoff and maximum resonance, record each voice’s oscillation frequency (VCF1\u20138: U67, U68, U62, U63, U57, U58, U52, U53, pin 9). This shows how far real chips differ.<\/li>\n<\/ol>\n

    4. Audio levels (priority)<\/h2>\n

    The emulation assumes a full-scale voice drives the CEM3328 to its rated 6.5 V p-p, because the DOC’s output current isn’t on the schematic. Measuring the real levels replaces that assumption.<\/p>\n

    Use one sustained note at maximum velocity, with the filter fully open and resonance off. Record peak-to-peak voltage at each point, then repeat with eight notes held.<\/p>\n\n\n\n\n\n\n\n\n\n\n
    Point<\/th>\nWhere<\/th>\n1 note (V p-p)<\/th>\n8 notes (V p-p)<\/th>\n<\/tr>\n<\/thead>\n
    DOC difference amp output<\/td>\nU46 pin 6 (U47 pin 3)<\/td>\n<\/td>\n<\/td>\n<\/tr>\n
    Voice 1 audio line (AF1)<\/td>\nU47 pin 13<\/td>\n<\/td>\n<\/td>\n<\/tr>\n
    CEM3328 signal input, voice 1<\/td>\nU67 pin 6<\/td>\n<\/td>\n<\/td>\n<\/tr>\n
    CEM3328 output, voice 1<\/td>\nU67 pin 9<\/td>\n<\/td>\n<\/td>\n<\/tr>\n
    Summer output<\/td>\nU56 pin 7<\/td>\n<\/td>\n<\/td>\n<\/tr>\n
    Audio out jack, volume at maximum<\/td>\nJ12<\/td>\n<\/td>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

    Please note the volume knob position and the sound used.<\/p>\n

    5. Filter calibration at boot<\/h2>\n

    Right after the OS loads, the firmware tunes each filter: it makes the filter oscillate, counts the cycles through the ADC, and adjusts the cutoff until 4 periods take about 130 ADC reads. MAME has no way to feed real filter output to its ADC, so it substitutes a modeled sine for each oscillating filter.<\/p>\n

      \n
    1. Trigger on the disk motor stopping after the OS load. Capture the summer output (U56 pin 7) and the ADC input path (U45 pin 13, COM X) for the next second.<\/li>\n
    2. Record the waveform’s amplitude and frequency at the ADC input. The firmware’s thresholds are $90 and $70, so the signal must swing well past both.<\/li>\n
    3. Record whether all eight voices oscillate together, or one at a time. The firmware leaves earlier voices at full resonance while tuning later ones, which suggests all together.<\/li>\n
    4. Record each voice’s final oscillation frequency once calibration ends, from its pin 9.<\/li>\n<\/ol>\n

      6. Keyboard controller link<\/h2>\n

      The keyboard’s R6500\/11 has an undumped internal ROM, so MAME imitates it from the main CPU’s side. Each key sends three bytes ($90 down or $80 up, key number 0\u201360, velocity) into the VIA shift register. The CPU acknowledges each byte with a low pulse on CA2. The timing and the velocity values are guesses.<\/p>\n

      Capture SCLK (U9 pin 18, CB1) and SDATA (U9 pin 19, CB2) on the two channels, then SCLK and SACK (U9 pin 39, CA2).<\/p>\n

        \n
      1. Shift clock rate, and the gap between bytes within one message.<\/li>\n
      2. Whether the controller waits for each CA2 pulse before sending the next byte, and the pulse’s width.<\/li>\n
      3. The velocity byte for a very soft, a medium and a very hard press of the same key. Decode it from SDATA, most significant bit first.<\/li>\n
      4. What the sustain pedal sends when pressed and released. The OS understands $B8 and $B9.<\/li>\n
      5. Any bytes sent at power-on, before a key is pressed, and the state of VIA PB4 (U9 pin 14, which also resets the controller) during boot.<\/li>\n<\/ol>\n

        Sending results<\/h2>\n

        Partial results help: sections 1, 3 and 4 alone would settle the biggest open questions.<\/p>\n